Vhdl for Synthesis

ELE591 – VHDL for Synthesis Issue 1. 0: 1st December 2010 The purpose of this laboratory experiment is to familiarise you with the principles of VHDL for synthesis targeted at programmable logic devices. You will observe how various VHDL descriptions result in Register Transfer Level (RTL) implementations and how these can be implemented within specific logic devices. The principles of back-annotation will also be explored and how this can be used to examine performance limitations of specific hardware resource mappings. This lab assumes you are already familiar with Xilinx ISE and ModelSim, given that ELE335 is a prerequisite for this module. If necessary, consult the ELE335 lab guide, which is included in the Coursework section of the ELE591 module webpage. Most of the VHDL files needed for this lab are also available from the same location. Exercise 1: Aim: To compare the results of different architectural descriptions for the same entity Steps: †¢ Create a project named â€Å"exercise1†. Add the file ex1a. vhd as a â€Å"VHDL module† †¢ Select the Spartan3 as the target device Compile and synthesise the VHDL description and examine the design report file, paying particular attention to the resource utilisation summary (and timing path analysis). Also examine the RTL design. †¢ Repeat with the files ex1b. vhd and ex1c. vhd and compare the results. Exercise 2: Aim: To illustrate the use of â€Å"don’t care† values in synthesis Steps: †¢ Create a proje ct named â€Å"exercise2†. Add the file docare. vhd as a â€Å"VHDL module† †¢ Compile and synthesise the design targeting the Spartan3 device †¢ Add the file dontcare. hd as a â€Å"VHDL module† and repeat the synthesis. †¢ Compare the report files. Exercise 3: Aim: To illustrate logic resource requirements for conditional versus mutually exclusive input conditions Steps: †¢ Create a project named â€Å"exercise3†. Add the file cond. vhd as a â€Å"VHDL module† †¢ Compile and synthesise the design targeting the Spartan3 device †¢ Add the file exclusiv. vhd as a â€Å"VHDL module† and repeat the synthesis. †¢ Compare the report files. Also compare the timings at the design logic level and at the place and route level. Exercise 4: Aim: To review resource and timing requirements of a complex reset function Steps: †¢ Create a project named â€Å"exercise4†. Add the file cntpt. vhd as a â€Å"VHDL module† †¢ Compile, synthesise and simulate the design targeting the Spartan3 device †¢ Review the report file paying particular attention to the reset equation. †¢ Now examine the file cntpt2. vhd which employs a synchronous complex reset. †¢ Attempt to simulate the designs and comment on the reset timing in both cases. Exercise 5: Aim: To compare CPLD and FPGA implementations of a FIFO design Steps: Create a project named â€Å"exercise5†. Add the file fifo. vhd as a â€Å"VHDL module† †¢ Compile and synthesise the design targeting the Spartan3 device †¢ Recompile the design for a Coolrunner2. †¢ Compare the report files and the resulting RTL layouts. †¢ Place and route both designs †¢ Compare the design files paying particular attention to the maximum operating frequency and the amount of resources used. Which timing parameter is the limiting factor on the operating frequency in each case? Exercise 6: Aim: To illustrate the effects of implicit memory Steps: †¢ Create a project named â€Å"exercise6†. Add the file memcont. vhd as a â€Å"VHDL module† †¢ Compile and synthesise the design targeting the Spartan3 device. †¢ Examine the report file. †¢ Add the file memcont2. vhd as a â€Å"VHDL module†. In this file the signal assignments for oe, we and addr are removed from under the reset condition. †¢ Compile and synthesise the design targeting the Spartan3 device. †¢ Compare the report file with that of the original design. Verify that implicit memory resulted in the creation of a combinatorial latch. Exercise 7: Aim: To illustrate the advantage of â€Å"one hot† encoding of large state-machines implemented in FPGA architectures Steps: †¢ Create a project named â€Å"exercise7†. Add the file onehot. vhd as a â€Å"VHDL module† †¢ Compile and synthesise the design targeting the Spartan3 device †¢ Place and route the design and record the number of logic cells required, the setup time, clock-to-output delay and maximum operating frequency. †¢ Now employ the file notonehot. vhd. This uses the synthesis tool to assign values to the various enumerated states. Compile and synthesise the updated design targeting the Spartan3 device. †¢ Place and route the design and record the number of logic cells required, the setup time, clock-to-output delay and maximum operating frequency. †¢ Compare the results with the original design. This series of experiments should be written up as an INDIVIDUAL formal lab report. The report will be limited to a maximum of 8 pages of main text (i. e. omitting title page etc). The hand-in date is the 17th December, unless you are informed otherwise.